# A 12 bit successive approximation type adc with digital error correction

As illustrated, the logic unit comprises circuitry, such as a processor P, a memory M, discrete circuitry DC and one or more logic gates, which may be employed alone or in various combinations to implement the logic unit Moreover, a reference voltage V REF is provided both to the inputs of the first and second conversion block and to the shift functional block As illustrated, the post-processing module comprises circuitry, such as a processor P, a memory M, discrete circuitry DC and one or more logic gates, which may be employed alone or in various combinations to implement the post-processing module In some embodiments, the logic unit and the post-processing module may be combined.

An exemplary embodiment of a circuit structure which may be employed in the embodiment of FIG. Particularly, such circuit structure comprises a capacitive-resistive digital-to-analog converter 10 also indicated as pseudo-differential C-R DAC or C-R DAC by those skilled in the art. Each of these arrays 11 , 12 is connected to a dedicated input terminal A,B of the comparator The SAR array 11 comprises an upper array 11 a including capacitors 32 C, 16 C, 8 C, 4 C, 2 C, C, C each having a respective terminal connected to the first dedicated input terminal A of comparator In addition, the SAR array 11 comprises a lower array 11 b including capacitors 8 C, 4 C, 2 C, C each having a respective terminal connected to a first common node F.

In the description which follows, reference is made to the circuit structure of FIG. The sub-lower array 13 comprises a plurality of resistors, particularly 17 resistors R 0 , R 1 ,. In addition, the resistors from R 0 to R 15 are equally sized so that to obtain partitioned voltages having voltage values of:. In more detail, resistors R 0 , R 1 ,. The resistive voltage divider 13 can be supplied by whatever supply voltage Vcc, in order to avoid draining current from the reference voltage V REF.

The voltages generated by the sub-lower array 13 are applied to both the capacitive lower array 11 b and the capacitive lower array 12 b of the DAC through a plurality of switches 20 connecting the resistors R 0 , R 1 ,. Such output voltage has generally a limited sourcing capability to charge the capacitors of C-R DAC This leads to longer settling times, especially during the first SAR tentatives since the capacitors of the upper array 11 a involved in this phase are large.

On the other hand, the sub-lower array 13 speeds up the settling times of the last SAR tentatives, provided that the sub-lower array 13 has a sufficient biasing current to guarantee an adequate settling level of the voltage of the third capacitors 21 , at the end of a given time. With reference to FIGS. In other words, this means that at the beginning of each tentative, only one bit of the bus is raised and the bit related to the previous tentative is kept to 1 or re-moved to 0 depending on the result of the previous tentative itself.

This code evolves through the scheduled comparisons: In this way, advantageously, metastability issues during the SAR phase may be excluded. This method step further comprises the operation of introducing a voltage shift Vs corresponding to half of a previous weigh, e. It should be observed that the two operations above are distinct from each other, but occur simultaneously.

In this way, the proposed method facilitates ensuring, that the search range extension is maintained unchanged in the passage from the first to the second conversion block. This occurrence gives to next comparison the faculty of correcting possible comparison errors done in the former tentatives. In addition, the proposed method facilitates ensuring that the center of this search range is shifted by an amount equal to half of the interval itself.

In equation 2 it is intended: With reference to the first binary code b 9 , b 8 ,. Moreover, with reference to the second binary code c 4 , c 3 ,. In the present example, the redundancy is implemented with reference to the 10 th and 11 th tentatives. Reference is made to FIG. In more detail, looking at the 10 th tentative, the LSB b 0 is set to logic level 1. This tentative voltage level corresponds to the result of the 9 th tentative increased by 2 4 codes LSBs.

In more detail, with reference to FIG. The difference from a classical SAR is that, in case this tentative bit is not confirmed, the value of the resulting code at the end of the 11 th tentative, before to raise up the bit related to the 12 th tentative, is 2 3 levels lower than the result of the previous tentative i. In other words, this tentative has a weight equal to 2 4 LSBs which is double with respect to the expected weight, i. This extension range attainment is through a code shift equal to 2 3 levels in the transition between the 10 th and the 11 th tentative, in the same time in which the bit of the 11 th tentative itself is raised up according to classical SAR approach.

This operation makes symmetric the range of the 11 th tentative with respect to the value achieved at the end of the 10 th tentative. The voltages generated by the sub-lower array 13 are applied to both the capacitive lower array 11 b and the capacitive lower array 12 b of the DAC through a plurality of switches 20 connecting the resistors R 0 , R 1 ,.

Such output voltage has generally a limited sourcing capability to charge the capacitors of C-R DAC This leads to longer settling times, especially during the first SAR tentatives since the capacitors of the upper array 11 a involved in this phase are large.

On the other hand, the sub-lower array 13 speeds up the settling times of the last SAR tentatives, provided that the sub-lower array 13 has a sufficient biasing current to guarantee an adequate settling level of the voltage of the third capacitors 21 , at the end of a given time. With reference to FIGS. In other words, this means that at the beginning of each tentative, only one bit of the bus is raised and the bit related to the previous tentative is kept to 1 or re-moved to 0 depending on the result of the previous tentative itself.

This code evolves through the scheduled comparisons: In this way, advantageously, metastability issues during the SAR phase may be excluded. This method step further comprises the operation of introducing a voltage shift Vs corresponding to half of a previous weigh, e. It should be observed that the two operations above are distinct from each other, but occur simultaneously.

In this way, the proposed method facilitates ensuring, that the search range extension is maintained unchanged in the passage from the first to the second conversion block. This occurrence gives to next comparison the faculty of correcting possible comparison errors done in the former tentatives.

In addition, the proposed method facilitates ensuring that the center of this search range is shifted by an amount equal to half of the interval itself. In equation 2 it is intended: With reference to the first binary code b 9 , b 8 ,. Moreover, with reference to the second binary code c 4 , c 3 ,.

In the present example, the redundancy is implemented with reference to the 10 th and 11 th tentatives. Reference is made to FIG. In more detail, looking at the 10 th tentative, the LSB b 0 is set to logic level 1. This tentative voltage level corresponds to the result of the 9 th tentative increased by 2 4 codes LSBs. In more detail, with reference to FIG. The difference from a classical SAR is that, in case this tentative bit is not confirmed, the value of the resulting code at the end of the 11 th tentative, before to raise up the bit related to the 12 th tentative, is 2 3 levels lower than the result of the previous tentative i.

In other words, this tentative has a weight equal to 2 4 LSBs which is double with respect to the expected weight, i. This extension range attainment is through a code shift equal to 2 3 levels in the transition between the 10 th and the 11 th tentative, in the same time in which the bit of the 11 th tentative itself is raised up according to classical SAR approach. This operation makes symmetric the range of the 11 th tentative with respect to the value achieved at the end of the 10 th tentative.

In the present example, the 11 th tentative appears to be a redundant one, because it can correct possible errors done in the previous ten tentatives present in the first bus as long as they are less than 8 LSBs. At the end of the SAR phase, the resulting code is evaluated by the equation 2: From the equation above, it is clear that the weights of 10 th and 11 th tentatives are the same, but, the 11 th one implies a voltage shift of half that weight, i.

The method and the corresponding redundancy has been implemented by the circuit structure of FIG. Voltage levels associated to the first common node SLS are quite straightforward, with the only peculiarity that they depend on bits c 2 , c 1 , c 0 and a fourth bit which is the logic OR between bits c 4 and c 3.

Particularly, voltage levels associated to the second common node SLG have the role to implement the redundancy. According to the values of bits c 4 and c 3 , the voltage values of the second common node SLG are configured to introduce a shifting of about 8 LSBs in the comparator input differential voltage.

On the contrary, if the setting of bit c 4 is confirmed by comparator , the 12 th tentative starts by setting the following bit c 3. For example, one can choose to reduce the current consumption, as well as to increase converter resolution, introducing a redundancy, to address voltage settlement issues that can arise.

In addition, an embodiment facilitates correction of potential comparison errors done in the former tentatives because of a lack of settling time by introducing only one redundant step. In this case, proper time can be reserved to perform such task, thus drastically reducing the risk associated to metastability. It should be clear that the generality of the principles of the presented method makes it applicable in different ways.

For example, since the least significant capacitances of the upper array 11 a of R-C DAC 10 are also involved in a fast settling tentative, a wider correction range could be achieved by introducing a similar redundant step on these capacitors. Some embodiments may take the form of or include computer program products. After decoding by thermometer decoder, M-Bits of address signals are delivered and supplied to the output data recording device After all conversion is completed, the completed signals and data are sent out.

In the second half of the cycle i. When the signals enter a second clock cycle i. In the second half cycle, it send out data 2 D time section and so on. Please refer to FIGS. Here for example, three bits are compared each time, for a total of three clock cycles, said DAC total bits is 9-Bits. When seven comparators are used, i. The number of comparators is 2 M -1 M: Therefore, the number of executed cycles is reduced, more comparators and a fewer capacitor array may be used to achieve the purpose of the subject invention that is upgrading of the frequency range in use to reach a high frequency of more than several MHz that may be applied in VIDEO applications.

In the case of phase 1, the comparators are in an Auto-zeroing mode, so, the voltage at the input point is VCM. The comparator employs fully-differential structure, though only single-way signals.

If one end receives a common-module voltage, it will still operate as for fully-differential operations.

In the application of traditional technology, data is compared bit by bit. So, the effective processing speed will restrict the applicable range. The range limit will be several dozens of kHz or hundreds of kHz. In the subject invention, several comparators are used, so that a multi-bits successive approximation ADC will produce several bits at a single CLOCK pulse, to reduce the number of CLOCK pulse cycles required for the conversion, to completely improve the conventional technology, and to extend the resolution by means of its capacitor coupling technique.